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Enabling Tower’s leading-edge BCD and RF technologies with Mentor Design Tools
December 3, 2020 UTC-7
As near-peer adversaries have been developing ever more complex electronic warfare technologies and carrying out exercises to jam allied communications, militaries must develop stronger and more resilient technology in order to withstand these challenges.
“We must work to ensure interoperability with allies and integration of the best technological developments from industry,” noted Brigadier General Bento Soares, Director CIS, Portuguese Army.
With this in mind, Mobile Deployable Communications 2021 will highlight the importance of interoperability by discussing international efforts, such as the Federated Mission Network and the Tactical Edge Networking programme.
The custom IC design tools from Mentor are ideally suited for analog IC design for BCD and RF applications and have enabled design teams to design from a single cockpit from schematic to tape-out. Tower has partnered with Mentor to provide our mutual customers a truly differentiated design environment.
“We must work to ensure interoperability with allies and integration of the best technological developments from industry,” noted Brigadier General Bento Soares, Director CIS, Portuguese Army.
With this in mind, Mobile Deployable Communications 2021 will highlight the importance of interoperability by discussing international efforts, such as the Federated Mission Network and the Tactical Edge Networking programme.
The custom IC design tools from Mentor are ideally suited for analog IC design for BCD and RF applications and have enabled design teams to design from a single cockpit from schematic to tape-out. Tower has partnered with Mentor to provide our mutual customers a truly differentiated design environment.
In this webinar, we’ll present an overview of the collaboration between Tower and Mentor with examples of both high-voltage and high-frequency design tools such as Tanner, AFS simulations, Calibre PERC and xRC highlighting their use for simulation, layout synthesis and best-in-class verification for high-yielding, high-performance and high-reliability ICsDate: Dec 3rd, 2020
Time: US/Pacific – 10:00 AM; Europe/London- 10:00AM
